1. Field of the Invention
The present invention relates to a power-good signal generator and a controller with power sequencing free.
2. Description of Related Art
Some of power-control integrated circuits have to monitor whether the output voltage is normal or not in the field of power management IC (integrated circuit) design. A power-good pin of a power management IC may provide a power-good signal when the output voltage is normal, such that the system may judge or proceed with the power-good signal. Especially in a complex system, such as a computer, a power sequencing and a restarting sequencing of the system have to be executed in a default sequence. FIG. 1 is a schematic diagram showing a power-good signal PG being used as a starting signal EN for a controller of a next stage system. Therefore, the controller of the next stage system can be prevented from being operated before the output voltage controlled by the power management IC is supplied stably. FIG. 2 is a schematic diagram showing a power-good signal modulated to be a starting signal EN for a controller of a next stage system. It is necessary that a phase and a level of the power-good signal PG are modulated suitably by a level shifter circuit between the adjacent stage systems as the starting signal EN of the next stage system. FIG. 3 is a schematic diagram showing a conventional level shifter circuit. The power-good signal PG is used to control a transistor M1 after being filtered and delayed by a resistance R1 and a capacitance C1. The transistor M1 is connected to a resistance R2 in series, and a transistor M2 is connected to a resistance R3 in series, and a connection node of the transistor M1 and the resistance R2 is connected to a gate of transistor M2. When the power-good signal PG is at a high level for a period of time, a voltage across the capacitance C1 is increased to turn on the transistor M1. At this time, the transistor M2 is turned off, so that the starting signal EN is at a high level.
In general, the power management IC does not have sufficient driving capability, and thus it cannot be ensured that the power management IC may drive the next stage circuit exactly and properly. Therefore, the power management IC may increase the driving capability of the power-good signal PG by using a power-good signal generator. FIG. 4 (a) is a schematic diagram showing a conventional power-good signal generator. The power-good signal generator comprises a resistance R4 and a transistor M5 connected in series, and the transistor M5 is controlled by a controller 10. The controller 10 is coupled to a first voltage source VDD to receive electric power for operating and turns off the transistor M5 when an output voltage of a converting circuit (not shown) controlled by the controller 10 reaches a predetermined potential. An end of the transistor R4 is coupled to a second voltage source VX, and the other end thereof is coupled to a drain of the transistor M5. A source of the transistor M5 is grounded and a gate thereof is coupled to the controller 10. The power-good signal generator generates the power-good signal PG at a connection node of the resistance R4 and the transistor M5 when the transistor M5 is turned off. The power-good signal generator may generate the power-good signal PG incorrectly when the first voltage source VDD and the second voltage source VX are provided in undesired sequence. FIG. 4 (b) is waveform diagram regarding the power-good signal generator shown in FIG. 4 (a) when a first voltage source VDD is provided after a second voltage source VX. The second voltage source VX is provided at time point t1, and the first voltage source VDD is provided later. At the time point t2, the voltage of the first voltage source VDD is increased to be enough to enable the controller 10 to turn on the transistor M5. Between the time points t1 and t2, the transistor M5 is turned off and thus the level of the power-good signal PG is increased with the voltage increase of the second voltage source VX until the transistor M5 is turned on at the time point t2. Namely, the power-good signal generator incorrectly generates the power-good signal PG. At the time point t3, the controller 10 determines that the output voltage of the converting circuit reaches the predetermined potential and then turns off the transistor M5 to output the power-good signal PG. The power-good signal PG incorrectly generated between the time points t1 and t2 may cause the next stage circuit to be started/operated incorrectly according to the power-good signal PG.